(1) Field of the Invention
The invention relates to a method of fabricating semiconductor devices, and more particularly, to the fabrication of high packing density, vertical CMOS devices in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
In current CMOS sub-micron technology, MOS transistors are formed horizontally across the surface of the semiconductor substrate. Such technology requires very tight control of the polysilicon line width critical dimension (CD). To achieve this precision, lithography and etch techniques must constantly be improved and are, in fact, limiting further process scaling.
A second approach to CMOS integration is to fabricate the transistor structures vertically into the semiconductor substrate. The footprint, or surface area requirement, for each transistor or logic device can be reduced by using the depth of the substrate. Of particular importance in such vertical integration schemes are issues such as metal interconnection, or wiring, process complexity, self-alignment, and compatibility with existing process techniques.
Several prior art approaches disclose methods to form vertical devices in the semiconductor substrate. U.S. Pat. No. 5,285,093 to Lage et al teaches a memory cell having a trench structure. A six layer stack of alternating p-type and n-type silicon is cross-sectioned by a trench. A layer of oxide is deposited. A polysilicon layer is deposited and forms a common gate overlying the p-type and n-type layers exposed by the trench. A memory device is constructed using this structure. U.S. Pat. No. 5,641,694 to Kenney discloses a method to form a vertical transistor and memory cell. A trench is etched through a stack of p-type and n-type layers. Additional epitaxial layers are grown inside the trench to form the transistor nodes. IBM Technical Disclosure Bulletin, May 1985, pp. 7046-7048 teaches a method to form a latch-up resistant CMOS inverter device. An n-channel transistor is formed at the bottom of a trench. A p-channel transistor is formed laterally, at the substrate surface, between trenches. U.S. Pat. No. 5,723,370 to Ning et al discloses a method to form vertical CMOS devices on a trench sidewall. The method does not take advantage of buried layers. Trenches are etched into the semiconductor substrate after formation of STI. Polysilicon is then deposited in the trench bottom. The polysilicon is then selectively ion implanted to form p-type and n-type regions. Gate oxide is deposited on the trench sidewalls. Ions are implanted, using an angled implantation technique, into the sidewalls of the trench to form channel regions. Additional levels of polysilicon and oxide are deposited into the trench to build up devices. U.S. Pat. No. 5,308,778 to Fitch et al discloses a method to form vertical transistors and logic gates inside of trenches. A stack of dielectric and polysilicon is formed overlying the substrate. A trench is etched through the stack. A diffusion region is formed at the trench bottom. Gate oxide is grown on the exposed polysilicon of the sidewalls. Doped silicon regions are then grown by epitaxy on the inside of the trench to thereby form the drain, channel, and source regions. U.S. Pat. No. 5,757,038 to Tiwari et al teaches a method to form ultra-thin channel FET devices. A three-layer stack is epitaxially grown overlying the substrate. A pillar structure is progressively formed by etching. U.S. Pat. No. 5,480,838 to Mitsui teaches a method to form a double-gate MIS transistor. Pillars are formed by etching into the semiconductor substrate. Ion implantation is used to form source and drain regions.
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating closely-spaced, CMOS inverters in the manufacture of integrated circuit devices.
A further object of the present invention is to provide a method to fabricate closely-spaced, CMOS inverters by forming vertical NMOS and PMOS transistors.
A yet further object of the present invention is to provide a method to fabricate vertical NMOS and PMOS transistors in a silicon implanted oxide substrate.
Another yet further object of the present invention is to fabricate vertical CMOS transistor using a trench to separate the NMOS and PMOS devices and to provide access to the common drain of the inverter pair and the sidewalls of the channel regions.
Another yet further object of the present invention is to connect the CMOS inverter pair using minimal area and utilizing self-aligned silicide (salicide) to reduce contact resistance.
Another object of the present invention is to achieve a novel, closely-spaced, CMOS inverter device using existing processes technology combined in a unique arrangement.
In accordance with the objects of this invention, a method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, a channel region, and a source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited overlying the gate oxide layer. The polysilicon layer is etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair in the manufacture of the integrated circuit device.
Also in accordance with the objects of this invention, a closely-spaced, vertical NMOS and PMOS transistor pair is achieved comprising, first, a substrate comprising silicon implanted oxide wherein an oxide layer is sandwiched between underlying and overlying silicon layers. A vertical NMOS transistor is in the overlying silicon layer. The vertical NMOS transistor comprises, first, a drain overlying the oxide layer. A channel region overlies the drain. A source overlies the channel region. A gate trench exposes a top surface of the drain and a vertical surface of the channel region. Finally, a gate comprises a polysilicon sidewall spacer adjacent to the vertical surface of the channel region with a gate oxide layer therebetween. Finally, a vertical PMOS transistor is in the overlying silicon layer. The PMOS transistor comprises, first, a drain overlying the oxide layer. The drain contacts the vertical NMOS transistor drain. A channel region overlies the drain. A source overlies the channel region. A gate trench exposes a top surface of the drain and a vertical surface of the channel region. Finally, a gate comprises a polysilicon sidewall spacer adjacent to the vertical surface of the channel region with a gate oxide layer therebetween.